 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by: DSP56004/D, Rev. 3 DSP56004 DSP56004ROM SYMPHONYTM AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS Motorola designed the SymphonyTM family of high-performance, programmable Digital Signal Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic, ATRAC, and Lucasfilm Home THX processing. Software for these applications is licensed by Motorola for integration into products like audio/video receivers, televisions, and automotive sound systems with such user-developed features as digital equalization and sound field processing. The DSP56004 is an MPU-style general purpose DSP, composed of an efficient 24-bit Digital Signal Processor core, program and data memories, various peripherals optimized for audio, and support circuitry. As illustrated in Figure 1, the DSP56000 core family compatible DSP is fed by program memory, two independent data RAMs and two data ROMs, a Serial Audio Interface (SAI), Serial Host Interface (SHI), External Memory Interface (EMI), dedicated I/O lines, on-chip Phase Lock Loop (PLL), and On-Chip Emulation (OnCETM) port. 4 General Purpose Input/ Output 9 Serial Audio Interface (SAI) 5 Serial Host Interface (SHI) 29 External Memory Interface (EMI) 16-Bit Bus 24-Bit Bus Program Memory* X Data Memory* Y Data Memory* 24-Bit DSP56000 Core Address Generation Unit PAB XAB YAB GDB Internal Data Bus Switch PDB XDB YDB OnCETM Port Clock Gen. Interrupt Control Program Decode Controller Program Control Unit Program Address Generator PLL Data ALU 24 x 24 + 56 56-bit MAC Two 56-Bit Accumulators 3 4 4 IRQA, IRQB, NMI, RESET *Refer to Table 1 for memory configurations. AA0248 Figure 1 DSP56004 Block Diagram (c)1996, 1997 MOTOROLA, INC. TABLE OF CONTENTS SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5 SIGNAL/CONNECTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 FOR TECHNICAL ASSISTANCE: Telephone: Email: Internet: 1-800-521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com Data Sheet Conventions This data sheet uses the following conventions: OVERBAR "asserted" "deasserted" Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN Note: Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage VIL/VOL VIH/VOH VIH/VOH VIL/VOL Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. ii DSP56004/D, Rev. 3 MOTOROLA DSP56004 Features FEATURES Digital Signal Processing Core * * * * * * * * * * * * * Efficient, object code compatible with the 24-bit DSP56000 core engine Up to 40.5 Million Instructions Per Second (MIPS)--24.7 ns instruction cycle at 81 MHz; up to 324 Million Operations Per Second (MOPS) at 81 MHz Highly parallel instruction set with unique DSP addressing modes Two 56-bit accumulators including extension byte Parallel 24 x 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) Double precision 48 x 48-bit multiply with 96-bit result in 6 instruction cycles 56-bit addition/subtraction in 1 instruction cycle Fractional and integer arithmetic with support for multiprecision arithmetic Hardware support for block floating-point Fast Fourier Transforms (FFT) Hardware nested DO loops Zero-overhead fast interrupts (2 instruction cycles) Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories Fabricated in high-density CMOS Memory * * On-chip modified Harvard architecture which permits simultaneous accesses to program and two data memories Bootstrap loading from Serial Host Interface or External Memory Interface Table 1 Memory Configuration (Word width is 24 bits) Program Part Type ROM DSP560041 DSP56004ROM2 Note: 1. 2. X Data ROM 256 256 RAM 256 256 Y Data ROM 256 256 RAM 256 256 RAM 512 256 Boot-strap ROM 64 64 None 2560 X data ROM is programmed with log2x and 2x tables; Y data ROM is programmed with a sine table. These ROMs may be factory programmed with data/program provided by the application developer. MOTOROLA DSP56004/D, Rev. 3 iii DSP56004 Features Peripheral and Support Circuits * Serial Audio Interface (SAI) includes two receivers and three transmitters, master or slave capability, implementation of I2S, Sony, and Matsushita audio protocols; and two sets of SAI interrupt vectors Serial Host Interface (SHI) features single master capability, 10-word receive FIFO, and support for 8-, 16-, and 24-bit words External Memory Interface (EMI), implemented as a peripheral supporting: - - - - * * * * * * * * * * Page-mode DRAMs (one or two chips): 64 K x 4, 256 K x 4, and 4 M x 4 bits SRAMs (one to four): 256 K x 8 bits Data bus may be 4 or 8 bits wide Data words may be 8, 12, 16, 20, or 24 bits wide * * Four dedicated, independent, programmable General Purpose Input/Output (GPIO) lines On-chip peripheral registers memory mapped in data memory space Three external interrupt request pins On-Chip Emulation (OnCE) port for unobtrusive, processor speedindependent debugging Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer for the core clock Power-saving Wait and Stop modes Fully static, HCMOS design for operating frequencies down to dc 80-pin plastic Quad Flat Pack surface-mount package; 14 x 14 x 2.20 mm (2.15-2.45 mm range); 0.65 mm lead pitch Complete pinout compatibility between DSP56004, DSP56004ROM, DSP56007, and DSP56009 for easy upgrades 5 V power supply iv DSP56004/D, Rev. 3 MOTOROLA DSP56004 Product Documentation PRODUCT DOCUMENTATION Table 2 lists the documents that provide a complete description of the DSP56004 and are required to design properly with the part. Documentation is available from a local Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature Distribution Center, or through the Motorola DSP home page on the Internet (the source for the latest information). Table 2 DSP56004 Documentation Document Name DSP56000 Family Manual DSP56004 User's Manual DSP56004 Technical Data Description of Content DSP56000 core family architecture and the 24-bit core processor and instruction set Memory, peripherals, and interfaces Electrical and timing specifications, and pin and package descriptions Order Number DSP56KFAMUM/AD DSP56004UM/AD DSP56004/D MOTOROLA DSP56004/D, Rev. 3 v DSP56004 Product Documentation vi DSP56004/D, Rev. 3 MOTOROLA SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS SIGNAL GROUPINGS The DSP56004 input and output signals are organized into the nine functional groups, as shown in Table 1-1. The individual signals are illustrated in Figure 1-1. Table 1-1 DSP56004 Functional Group Signal Allocations Functional Group Power (VCC) Ground (GND) Phase Lock Loop (PLL) External Memory Interface (EMI) Interrupt and Mode Control Serial Host Interface (SHI) Serial Audio Interface (SAI) General Purpose Input/Output (GPIO) On-Chip Emulation (OnCE) port Total Number of Signals 9 13 3 29 4 5 9 4 4 80 Detailed Description Table 1-2 Table 1-3 Table 1-4 Table 1-5 and Table 1-6 Table 1-7 Table 1-8 Table 1-9 and Table 1-10 Table 1-11 Table 1-12 MOTOROLA DSP56004/D, Rev. 3 1-1 Signal/Connection Descriptions Signal Groupings Power Inputs VCCP 3 VCCQ 2 VCCA VCCD 2 VCCS Ground GNDP GNDQ GNDA GNDD GNDS DSP56007 MOSI/HA0 Port B Serial Host Interface SS/HA2 MISO/SDA SCK/SCL HREQ 3 4 2 3 Port C Serial Audio Interface WSR SCKR SDI0 SDI1 WST PCAP PINIT EXTAL PLL Rec0 Rec1 MA0-MA14 MD0-MD7 MA15/MCS3 MA16/MCS2/MCAS MA17/MCS1/MRAS MCS0 MWR MRD MODC/NMI MODB/IRQB MODA/IRQA RESET 15 8 SCKT Tran0 Tran1 Tran2 Port A External Memory Interface GPIO SDO0 SDO1 SDO2 4 GPIO0-GPIO3 DSCK/OS1 Mode/Interrupt Control Reset 80 signals AA0249G OnCETM Port DSI/OS0 DSO DR Figure 1-1 DSP56004 SIgnals 1-2 DSP56004/D, Rev. 3 MOTOROLA Signal/Connection Descriptions Power POWER Table 1-2 Power Inputs Power Name VCCP Description PLL Power--VCCP provides isolated power for the Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. Quiet Power--VCCQ provides isolated power for the internal processing logic. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. Address Bus Power--VCCA provides isolated power for sections of the address bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. Data Bus Power--VCCD provides isolated power for sections of the data bus I/O drivers. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. Serial Interface Power--VCCS provides isolated power for the SHI and SAI. This input must be tied externally to all other chip power inputs. The user must provide adequate external decoupling capacitors. VCCQ VCCA VCCD VCCS GROUND Table 1-3 Grounds Ground Name GNDP Description PLL Ground--GNDP is ground dedicated for PLL use. The connection should be provided with an extremely low-impedance path to ground. VCCP should be bypassed to GNDP by a 0.47 F capacitor located as close as possible to the chip package. Quiet Ground--GNDQ provides isolated ground for the internal processing logic. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Address Bus Ground--GNDA provides isolated ground for sections of the address bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Data Bus Ground--GNDD provides isolated ground for sections of the data bus I/O drivers. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. Serial Interface Ground--GNDS provides isolated ground for the SHI and SAI. This connection must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. GNDQ GNDA GNDD GNDS MOTOROLA DSP56004/D, Rev. 3 1-3 Signal/Connection Descriptions Clock and PLL signals CLOCK AND PLL SIGNALS Note: While the PLL on this DSP is identical to the PLL described in the DSP56000 Family Manual, two of the signals have not been implemented externally. Specifically, there is no PLOCK signal or CKOUT signal available. Therefore, the internal clock is not directly accessible and there is no external indication that the PLL is locked. These signals were omitted to reduce the number of pins and allow this DSP to be put in a smaller, less expensive package. Table 1-4 Clock and PLL Signals Signal Name EXTAL Signal Type Input State during Reset Input Signal Description External Clock/Crystal--This input should be connected to an external clock source. If the PLL is enabled, this signal is internally connected to the on-chip PLL. The PLL can multiply the frequency on the EXTAL pin to generate the internal DSP clock. The PLL output is divided by two to produce a four-phase instruction cycle clock, with the minimum instruction time being two PLL output clock periods. If the PLL is disabled, EXTAL is divided by two to produce the four-phase instruction cycle clock. PLL Filter Capacitor--This input is used to connect a highquality (high "Q" factor) external capacitor needed for the PLL filter. The capacitor should be as close as possible to the DSP with heavy, short traces connecting one terminal of the capacitor to PCAP and the other terminal to VCCP. The required capacitor value is specified in Table 2-6 on page 2-6. Note: When short lock time is critical, low dielectric absorption capacitors such as polystyrene, polypropylene, or teflon are recommended. PCAP Input Input If the PLL is not used (i.e., it remains disabled at all times), there is no need to connect a capacitor to the PCAP pin. It may remain unconnected, or be tied to either Vcc or GND. PINIT Input Input PLL Initialization (PINIT)--During the assertion of hardware reset, the value on the PINIT line is written into the PEN bit of the PCTL register. When set, the PEN bit enables the PLL by causing it to derive the internal clocks from the PLL voltage controlled oscillator output. When the bit is cleared, the PLL is disabled and the DSP's internal clocks are derived from the clock connected to the EXTAL signal. After hardware RESET is deasserted, the PINIT signal is ignored. 1-4 DSP56004/D, Rev. 3 MOTOROLA Signal/Connection Descriptions External Memory Interface (EMI) EXTERNAL MEMORY INTERFACE (EMI) Table 1-5 External Memory Interface (EMI) Signals Signal Name MA0-MA14 Signal Type Output State during Reset Signal Description Memory Address Lines 0-14--The MA0-MA10 lines provide the multiplexed row/column addresses for DRAM accesses. Lines MA0-MA14 provide the non-multiplexed address lines 0-14 for SRAM accesses. Memory Address Line 15 (MA15)--This line functions as the non-multiplexed address line 15. Memory Chip Select 3 (MCS3)--For SRAM accesses, this line functions as memory chip select 3. Output Table 1-6 MA15 Output Table 1-6 MCS3 MA16 Table 1-6 Memory Address Line 16 (MA16)--This line functions as the non-multiplexed address line 16 or as memory chip select 2 for SRAM accesses. Memory Chip Select 2 (MCS2)--For SRAM access, this line functions as memory chip select 2. Memory Column Address Strobe (MCAS)--This line functions as the Memory Column Address Strobe (MCAS) during DRAM accesses. MCS2 MCAS MA17 Output Table 1-6 Memory Address Line 17 (MA17)--This line functions as the non-multiplexed address line 17. Memory Chip Select 1 (MCS1)--This line functions as chip select 1 for SRAM accesses. Memory Row Address Strobe (MRAS)--This line also functions as the Memory Row Address Strobe during DRAM accesses. MCS1 MRAS MCS0 MWR MRD Output Output Output Table 1-6 Table 1-6 Table 1-6 Memory Chip Select 0--This line functions as memory chip select 0 for SRAM accesses. Memory Write Strobe--This line is asserted when writing to external memory. Memory Read Strobe--This line is asserted when reading external memory. MOTOROLA DSP56004/D, Rev. 3 1-5 Signal/Connection Descriptions External Memory Interface (EMI) Table 1-5 External Memory Interface (EMI) Signals (Continued) Signal Name MD0-MD7 Signal Type Bidirectional State during Reset Tri-stated Signal Description Data Bus--These signals provide the bidirectional data bus for EMI accesses. They are inputs during reads from external memory, outputs during writes to external memory, and tristated if no external access is taking place. If the data bus width is defined as four bits wide, only signals MD0-MD3 are active, while signals MD4-MD7 remain tri-stated. While tri-stated, MD0-MD7 are disconnected from the pins and do not require external pull-ups. . Table 1-6 EMI States during Reset and Stop States Operating Mode Signal Hardware Reset MA0-MA14 MA15 MCS3 MA16 MCS2 MCAS: DRAM refresh disabled DRAM refresh enabled MA17 MCS1 MRAS: Driven High Driven High Driven High Driven High Driven High Software Reset Individual Reset Previous State Driven High Driven High Driven High Driven High Previous State Previous State Driven High Previous State Driven High Stop Mode Previous State Previous State Driven High Previous State Driven High Driven High Driven High Driven High Driven High Driven High Driven High Driven High Driven High Driven High Driven Low Previous State Driven High Driven High Driven High Previous State Driven High DRAM refresh disabled DRAM refresh enabled MCS0 MWR MRD Driven High Driven High Driven High Driven High Driven High Driven High Driven High Driven High Driven High Driven High Driven High Driven Low Driven High Driven High Driven High Driven High Driven High Driven High Driven High Driven High 1-6 DSP56004/D, Rev. 3 MOTOROLA Signal/Connection Descriptions Interrupt and Mode Control INTERRUPT AND MODE CONTROL The interrupt and mode control signals select the DSP's operating mode as it comes out of hardware reset and receives interrupt requests from external sources after reset. Table 1-7 Interrupt and Mode Control Signals Signal Name MODA Signal Type Input State during Reset Signal Description Input (MODA) Mode Select A--This input signal has three functions: * * * to work with the MODB and MODC signals to select the DSP's initial operating mode, to allow an external device to request a DSP interrupt after internal synchronization, and to turn on the internal clock generator when the DSP is in the Stop processing state, causing the DSP to resume processing. MODA is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODA signal changes to the external interrupt request IRQA. The DSP operating mode can be changed by software after reset. IRQA External Interrupt Request A (IRQA)--The IRQA input is a synchronized external interrupt request. It may be programmed to be level-sensitive or negative-edgetriggered. When the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQA will generate multiple interrupts also increases. While the DSP is in the Stop mode, asserting IRQA gates on the oscillator and, after a clock stabilization delay, enables clocks to the processor and peripherals. Hardware reset causes this input to function as MODA. MOTOROLA DSP56004/D, Rev. 3 1-7 Signal/Connection Descriptions Interrupt and Mode Control Table 1-7 Interrupt and Mode Control Signals (Continued) Signal Name MODB Signal Type Input State during Reset Signal Description Input (MODB) Mode Select B--This input signal has two functions: * * to work with the MODA and MODC signals to select the DSP's initial operating mode, and to allow an external device to request a DSP interrupt after internal synchronization. MODB is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODB signal changes to the external interrupt request IRQB. The DSP operating mode can be changed by software after reset. IRQB External Interrupt Request B (IRQB)--The IRQB input is a synchronized external interrupt request. It may be programmed to be level-sensitive or negative-edgetriggered. When the signal is edge-triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQB will generate multiple interrupts also increases. Hardware reset causes this input to function as MODB. 1-8 DSP56004/D, Rev. 3 MOTOROLA Signal/Connection Descriptions Interrupt and Mode Control Table 1-7 Interrupt and Mode Control Signals (Continued) Signal Name MODC Signal Type Input, edgetriggered State during Reset Signal Description Input (MODC) Mode Select C--This input signal has two functions: * * to work with the MODA and MODB signals to select the DSP's initial operating mode, and to allow an external device to request a DSP interrupt after internal synchronization. MODC is read and internally latched in the DSP when the processor exits the Reset state. The logic state present on the MODA, MODB, and MODC pins selects the initial DSP operating mode. Several clock cycles after leaving the Reset state, the MODC signal changes to the Non-Maskable Interrupt request, NMI. The DSP operating mode can be changed by software after reset. NMI Non-Maskable Interrupt Request--The NMI input is a negative-edge-triggered external interrupt request. This is a level 3 interrupt that can not be masked out. Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on NMI will generate multiple interrupts also increases. Hardware reset causes this input to function as MODC. input active RESET--This input causes a direct hardware reset of the processor. When RESET is asserted, the DSP is initialized and placed in the Reset state. A Schmitt-trigger input is used for noise immunity. When the reset signal is deasserted, the initial DSP operating mode is latched from the MODA, MODB, and MODC signals. The DSP also samples the PINIT signal and writes its status into the PEN bit of the PLL Control Register. When the DSP comes out of the Reset state, deassertion occurs at a voltage level and is not directly related to the rise time of the RESET signal. However, the probability that noise on RESET will generate multiple resets increases with increasing rise time of the RESET signal. For proper hardware reset to occur, the clock must be active, since a number of clock ticks are required for proper propagation of the hardware Reset state. RESET MOTOROLA DSP56004/D, Rev. 3 1-9 Signal/Connection Descriptions Serial Host Interface (SHI) SERIAL HOST INTERFACE (SHI) The Serial Host Interface (SHI) has five I/O signals, which may be configured to operate in either SPI or I2C mode. Table 1-8 lists the SHI signals. Table 1-8 Serial Host Interface (SHI) signals Signal Name Signal Type Input or Output State during Reset Tri-stated Signal Description SCK SPI Serial Clock (SCK)--The SCK signal is an output when the SPI is configured as a master, and a Schmitttrigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator. When the SPI is configured as a slave, the SCK signal is an input, and the clock signal from the external master synchronizes the data transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the Slave Select (SS) signal is not asserted. In both the master and slave SPI devices, data is shifted on one edge of the SCK signal and is sampled on the opposite edge where data is stable. Edge polarity is determined by the SPI transfer protocol. I2C Serial Clock (SCL)--SCL carries the clock for bus transactions in the I2C mode. SCL is a Schmitt-trigger input when configured as a slave, and an open-drain output when configured as a master. SCL should be connected to VCC through a pull-up resistor. The maximum allowed internally generated bit clock frequency is Fosc/4 for the SPI mode and Fosc/6 for the I2C mode where Fosc is the clock on EXTAL. The maximum allowed externally generated bit clock frequency is Fosc/3 for the SPI mode and Fosc/5 for the I2C mode. This signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). SCL Input or Output 1-10 DSP56004/D, Rev. 3 MOTOROLA Signal/Connection Descriptions Serial Host Interface (SHI) Table 1-8 Serial Host Interface (SHI) signals (Continued) Signal Name Signal Type Input or Output State during Reset Tri-stated Signal Description MISO SPI Master-In-Slave-Out (MISO)--When the SPI is configured as a master, MISO is the master data input line. The MISO signal is used in conjunction with the MOSI signal for transmitting and receiving serial data. This signal is a Schmitt-trigger input when configured for the SPI Master mode, an output when configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave mode when SS is deasserted. I2C Serial Data and Acknowledge (SDA)--In I2C mode, SDA is a Schmitt-trigger input when receiving and an open-drain output when transmitting. SDA should be connected to VCC through a pull-up resistor. SDA carries the data for I2C transactions. The data in SDA must be stable during the high period of SCL. The data in SDA is only allowed to change when SCL is low. When the bus is free, SDA is high. The SDA line is only allowed to change during the time SCL is high in the case of Start and Stop events. A high-to-low transition of the SDA line while SCL is high is an unique situation, and is defined as the Start event. A low-to-high transition of SDA while SCL is high is an unique situation, and is defined as the Stop event. Note: This line is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). SDA Input or Output MOSI Input or Output Tri-stated SPI Master-Out-Slave-In (MOSI)--When the SPI is configured as a master, MOSI is the master data output line. The MOSI signal is used in conjunction with the MISO signal for transmitting and receiving serial data. MOSI is the slave data input line when the SPI is configured as a slave. This signal is a Schmitt-trigger input when configured for the SPI Slave mode. I2C Slave Address 0 (HA0)--This signal uses a Schmitttrigger input when configured for the I2C mode. When configured for I2C Slave mode, the HA0 signal is used to form the slave device address. HA0 is ignored when the SHI is configured for the I2C Master mode. Note: This signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). HA0 Input MOTOROLA DSP56004/D, Rev. 3 1-11 Signal/Connection Descriptions Serial Host Interface (SHI) Table 1-8 Serial Host Interface (SHI) signals (Continued) Signal Name Signal Type Input State during Reset Tri-stated Signal Description SS SPI Slave Select (SS)--This signal is an active low Schmitt-trigger input when configured for the SPI mode. When configured for the SPI Slave mode, this signal is used to enable the SPI slave for transfer. When configured for the SPI Master mode, this signal should be kept deasserted. If it is asserted while configured as SPI master, a bus error condition will be flagged. I2C Slave Address 2 (HA2)--This signal uses a Schmitt-trigger input when configured for the I2C mode. When configured for the I2C Slave mode, the HA2 signal is used to form the slave device address. HA2 is ignored in the I2C Master mode. If SS is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance state. Note: This signal is tri-stated during hardware reset, software reset, or individual reset (no need for external pull-up in this state). HA2 Input HREQ Input or Output Tri-stated Host Request--This signal is an active low Schmitttrigger input when configured for the Master mode, but an active low output when configured for the Slave mode. When configured for the Slave mode, HREQ is asserted to indicate that the SHI is ready for the next data word transfer and deasserted at the first clock pulse of the new data word transfer. When configured for the Master mode, HREQ is an input and when asserted by the external slave device, it will trigger the start of the data word transfer by the master. After finishing the data word transfer, the master will await the next assertion of HREQ to proceed to the next transfer. Note: This signal is tri-stated during hardware, software, individual reset, or when the HREQ[1:0] bits (in the HCSR) are cleared (no need for external pull-up in this state). 1-12 DSP56004/D, Rev. 3 MOTOROLA Signal/Connection Descriptions Serial Audio Interface (SAI) SERIAL AUDIO INTERFACE (SAI) The SAI is composed of separate receiver and transmitter sections. SAI Receiver Section Table 1-9 Serial Audio Interface (SAI) Receiver signals Signal Name SDI0 Signal Type Input State during Reset Tri-stated Signal Description Serial Data Input 0--While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. SDI0 is the serial data input for receiver 0. Note: This signal is high impedance during hardware or software reset, while receiver 0 is disabled (R0EN = 0), or while the DSP is in the Stop state. SDI1 Input Tri-stated Serial Data Input 1--While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. SDI1 is the serial data input for receiver 1. Note: This signal is high impedance during hardware or software reset, while receiver 1 is disabled (R1EN = 0), or while the DSP is in the Stop state. SCKR Input or Output Tri-stated Receive Serial Clock--SCKR is an output if the receiver section is programmed as a master, and a Schmitt-trigger input if programmed as a slave. While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. Note: SCKR is high impedance if all receivers are disabled (individual reset) and during hardware or software reset, or while the DSP is in the Stop state. MOTOROLA DSP56004/D, Rev. 3 1-13 Signal/Connection Descriptions Serial Audio Interface (SAI) Table 1-9 Serial Audio Interface (SAI) Receiver signals (Continued) Signal Name WSR Signal Type Input or Output State during Reset Tri-stated Signal Description Word Select Receive (WSR)--WSR is an output if the receiver section is configured as a master, and a Schmitt-trigger input if configured as a slave. WSR is used to synchronize the data word and to select the left/right portion of the data sample. Note: WSR is high impedance if all receivers are disabled (individual reset), during hardware reset, during software reset, or while the DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the signal and no external pull-up is necessary. 1-14 DSP56004/D, Rev. 3 MOTOROLA Signal/Connection Descriptions Serial Audio Interface (SAI) SAI Transmitter Section Table 1-10 Serial Audio Interface (SAI) Transmitter signals Signal Name SDO0 Signal Type Output State during Reset Driven High Signal Description Serial Data Output 0 (SDO0)--SDO0 is the serial output for transmitter 0. SDO0 is driven high if transmitter 0 is disabled, during individual reset, hardware reset, and software reset, or when the DSP is in the Stop state. Serial Data Output 1 (SDO1)--SDO1 is the serial output for transmitter 1. SDO1 is driven high if transmitter 1 is disabled, during individual reset, hardware reset and software reset, or when the DSP is in the Stop state. Serial Data Output 2 (SDO2)--SDO2 is the serial output for transmitter 2. SDO2 is driven high if transmitter 2 is disabled, during individual reset, hardware reset and software reset, or when the DSP is in the Stop state. Serial Clock Transmit (SCKT)--This signal provides the clock for the SAI. SCKT can be an output if the transmit section is configured as a master, or a Schmitt-trigger input if the transmit section is configured as a slave. When the SCKT is an output, it provides an internally generated SAI transmit clock to external circuitry. When the SCKT is an input, it allows external circuitry to clock data out of the SAI. Note: SCKT is high impedance if all transmitters are disabled (individual reset), during hardware reset, software reset, or while the DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. SDO1 Output Driven High SDO2 Output Driven High SCKT Input or Output Tri-stated WST Input or Output Tri-stated Word Select Transmit (WST)--WST is an output if the transmit section is programmed as a master, and a Schmitttrigger input if it is programmed as a slave. WST is used to synchronize the data word and select the left/right portion of the data sample. Note: WST is high impedance if all transmitters are disabled (individual reset), during hardware or software reset, or while the DSP is in the Stop state. While in the high impedance state, the internal input buffer is disconnected from the pin and no external pull-up is necessary. MOTOROLA DSP56004/D, Rev. 3 1-15 Signal/Connection Descriptions General Purpose I/O GENERAL PURPOSE I/O Table 1-11 General Purpose I/O (GPIO) Signals Signal Name GPIO0- GPIO3 Signal Type Standard Output, Open-drain Output, or Input State during Reset Disconnected Signal Description GPIO lines can be used for control and handshake functions between the DSP and external circuitry. Each GPIO line can be configured individually as disconnected, open-drain output, standard output, or an input. Note: Hardware reset or software reset configures all the GPIO lines as disconnected (external circuitry connected to these pins may need pullups until the pins are configured for operation). ON-CHIP EMULATION (OnCETM) PORT There are four signals associated with the OnCE port controller and its serial interface. Table 1-12 On-Chip Emulation Port Signals Signal Name DSI Signal Type Input State during Reset Output, Driven Low Signal Description Debug Serial Input (DSI)--The DSI signal is the signal through which serial data or commands are provided to the OnCE port controller. The data received on the DSI signal will be recognized only when the DSP has entered the Debug mode of operation. Data must have valid TTL logic levels before the serial clock falling edge. Data is always shifted into the OnCE port Most Significant Bit (MSB) first. Operating Status 0 (OS0)--When the DSP is not in the Debug mode, the OS0 signal provides information about the DSP status if it is an output and used in conjunction with the OS1 signal. When switching from output to input, the signal is tri-stated. Note: If the OnCE port is in use, an external pull-down resistor should be attached to the DSI/OS0 signal. If the OnCE port is not in use, the resistor is not required. OS0 Output 1-16 DSP56004/D, Rev. 3 MOTOROLA Signal/Connection Descriptions On-Chip Emulation (OnCETM) Port Table 1-12 On-Chip Emulation Port Signals (Continued) Signal Name DSCK Signal Type Input State during Reset Output, Driven Low Signal Description Debug Serial Clock (DSCK)--The DSCK/OS1 signal, when an input, is the signal through which the serial clock is supplied to the OnCE port. The serial clock provides pulses required to shift data into and out of the OnCE port. Data is clocked into the OnCE port on the falling edge and is clocked out of the OnCE port on the rising edge. Operating Status 1 (OS1)--If the OS1 signal is an output and used in conjunction with the OS0 signal, it provides information about the DSP status when the DSP is not in the Debug mode. The debug serial clock frequency must be no greater than 1/8 of the processor clock frequency. The signal is tri-stated when it is changing from input to output. Note: If the OnCE port is in use, an external pull-down resistor should be attached to the DSCK/OS1 pin. If the OnCE port is not in use, the resistor is not required. OS1 Output DSO Output Driven High Debug Serial Output (DSO)--The DSO line provides the data contained in one of the OnCE port controller registers as specified by the last command received from the command controller. The Most Significant Bit (MSB) of the data word is always shifted out of the OnCE port first. Data is clocked out of the OnCE port on the rising edge of DSCK. The DSO line also provides acknowledge pulses to the external command controller. When the DSP enters the Debug mode, the DSO line will be pulsed low to indicate that the OnCE port is waiting for commands. After receiving a read command, the DSO line will be pulsed low to indicate that the requested data is available and the OnCE port is ready to receive clock pulses in order to deliver the data. After receiving a write command, the DSO line will be pulsed low to indicate that the OnCE port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided. Note: During hardware reset and when idle, the DSO line is held high. MOTOROLA DSP56004/D, Rev. 3 1-17 Signal/Connection Descriptions On-Chip Emulation (OnCETM) Port Table 1-12 On-Chip Emulation Port Signals (Continued) Signal Name DR Signal Type Input State during Reset Input Signal Description Debug Request (DR)--The debug request input provides a means of entering the Debug mode of operation. This signal, when asserted (pulled low), will cause the DSP to finish the current instruction being executed, to save the instruction pipeline information, to enter the Debug mode, and to wait for commands to be entered from the debug serial input line. While the DSP is in the Debug mode, the user can reset the OnCE port controller by asserting DR, waiting for an acknowledge pulse on DSO, and then deasserting DR. It may be necessary to reset the OnCE port controller in cases where synchronization between the OnCE port controller and external circuitry is lost. Asserting DR when the DSP is in the Wait or the Stop mode, and keeping it asserted until an acknowledge pulse in the DSP is produced, puts the DSP into the Debug mode. After receiving the acknowledge pulse, DR must be deasserted before sending the first OnCE port command. For more information, see Methods Of Entering The Debug Mode in the DSP56000 Family Manual. Note: If the OnCE port is not in use, an external pull-up resistor should be attached to the DR line. 1-18 DSP56004/D, Rev. 3 MOTOROLA SECTION 2 SPECIFICATIONS INTRODUCTION The DSP56004 is fabricated in high density CMOS with Transistor-Transistor Logic (TTL) compatible inputs and outputs. MAXIMUM RATINGS CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification will never occur in the same device that has a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. MOTOROLA DSP56004/D, Rev. 3 2-1 Specifications Thermal characteristics Table 2-1 Maximum Ratings (GND = 0 Vdc) Rating Supply Voltage All Input Voltages: * 50 and 66 MHz * 81 MHz Current Drain per Pin excluding VCC and GND Operating Temperature Range: * 50 and 66 MHz * 81 MHz Storage Temperature Symbol VCC VIN Value -0.3 to +7.0 (GND - 0.5) to (VCC + 0.5) (GND - 0.25) to (VCC + 0.25) 10 -40 to +125 -40 to +120 -55 to +125 mA C C C Unit V V I TJ TSTG THERMAL CHARACTERISTICS Table 2-2 Thermal Characteristics Characteristic Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance2 Thermal characterization parameter Notes: 1. Symbol RJA or JA RJC or JC JT QFP Value3 70.4 16.4 3.2 QFP Value4 45.1 -- -- Unit C/W C/W C/W 2. 3. 4. Junction-to-ambient thermal resistance is based on measurements on a horizontal-single-sided Printed Circuit Board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111) Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G3088, with the exception that the cold plate temperature is used for the case temperature. These are measured values. See note 1 for test board conditions. These are measured values; testing is not complete. Values were measured on a non-standard four-layer thermal test board (two internal planes) at one watt in a horizontal configuration. 2-2 DSP56004/D, Rev. 3 MOTOROLA Specifications DC Electrical Characteristics DC ELECTRICAL CHARACTERISTICS Table 2-3 DC Electrical Characteristics 50 MHz Characteristics Supply voltage Input high voltage * EXTAL * RESET * MODA, MODB, MODC * SHI inputs1 * All other inputs Symbol Min Typ Max VCC VIHC VIHR VIHM VIHS VIH VILC VILM VILS VIL IIN 4.5 4.0 2.5 3.5 0.7 x VCC 2.0 -0.5 -0.5 -0.5 -0.5 -1 5.0 -- -- -- -- -- -- -- -- -- -- 5.5 VCC VCC VCC VCC VCC 0.6 2.0 0.3 x VCC 0.8 1 Min Typ Max 4.5 4.0 2.5 3.5 0.7 x VCC 2.0 -0.5 -0.5 -0.5 -0.5 -1 5.0 -- -- -- -- -- -- -- -- -- -- 5.5 VCC VCC VCC VCC VCC 0.6 2.0 0.3 x VCC 0.8 1 Min 4.75 4.0 2.5 3.5 0.7 x VCC 2.0 -0.25 -0.25 -0.25 -0.25 -1 Typ 5.0 -- -- -- -- -- -- -- -- -- -- Max 5.25 VCC VCC VCC VCC VCC 0.6 2.0 0.3 x VCC 0.8 1 V V V V V V V V V V A A A V V 66 MHz 81 MHz Unit Input low voltage * EXTAL * MODA, MODB, MODC * SHI inputs1 * All other inputs Input leakage current * EXTAL, RESET, MODA, MODB, MODC, DR * Other Input Pins (@ 2.4 V/0.4 V) High impedance (off-state) input current (@ 2.4 V / 0.4 V) Output high voltage (IOH = -0.4 mA) Output low voltage (IOL = 3.2 mA) SCK/SCL IOL = 6.7 mA MISO/SDA IOL = 6.7 mA HREQ IOL = 6.7 mA Internal Supply Current * Normal mode * Wait mode * Stop mode2 -10 ITSI VOH VOL -10 2.4 -- -- -- -- -- 10 10 -- 0.4 -10 -10 2.4 -- -- -- -- -- 10 10 -- 0.4 -10 -10 2.4 -- -- -- -- -- 10 10 -- 0.4 ICCI ICCW ICCS -- -- -- 75 14 5 1054 25 110 -- -- -- 103 18 5 1304 30 110 -- -- -- 120 20 5 1554 30 110 mA mA A MOTOROLA DSP56004/D, Rev. 3 2-3 Specifications AC Electrical Characteristics Table 2-3 DC Electrical Characteristics 50 MHz Characteristics PLL supply current Input capacitance3 Notes: 1. 2. 3. 4. 66 MHz Min Typ Max -- -- 1.0 10 1.5 -- Min -- -- 81 MHz Unit Typ 1.2 10 Max 2.0 -- mA pF Symbol Min Typ Max -- CIN -- 0.7 10 1.1 -- The SHI inputs are: MOSI/HA0, SS/HA2, MISO/SDA, SCK/SCL, and HREQ. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). PLL signals are disabled during Stop state. Periodically sampled and not 100% tested Maximum values are derived using the methodology described in Section 4. Actual maximums are application dependent and may vary widely from these numbers. AC ELECTRICAL CHARACTERISTICS The timing waveforms in the AC Electrical Characteristics are tested with a VIL maximum of 0.5 V and a VIH minimum of 2.4 V for all pins, except EXTAL, RESET, MODA, MODB, MODC, and SHI pins (MOSI/HA0, SS/HA2, MISO/SDA, SCK/ SCL, HREQ). These pins are tested using the input levels set forth in the DC Electrical Characteristics. AC timing specifications that are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal's transition. DSP56004 output levels are measured with the production test machine VOL and VOH reference levels set at 0.8 V and 2.0 V, respectively. All output delays are given for a 50 pF load unless otherwise specified. For load capacitance greater than 50 pF, the drive capability of the output pins typically decreases linearly: 1. At 1.5 ns per 10 pF of additional capacitance at all output pins except MOSI/ HA0, MISO/SDA, SCK/SCL, HREQ 2. At 1.0 ns per 10 pF of additional capacitance at output pins MOSI/HA0, MISO/SDA, SCK/SCL, HREQ (in SPI mode only) 2-4 DSP56004/D, Rev. 3 MOTOROLA Specifications Internal Clocks INTERNAL CLOCKS For each occurrence of TH, TL, TC or Icyc, substitute with the numbers in Table 2-4. Table 2-4 Internal Clocks Expression Characteristics Internal Operation Frequency Internal Clock High Period * with PLL disabled * with PLL enabled and MF 4 * with PLL enabled and MF > 4 Internal Clock Low Period * with PLL disabled * with PLL enabled and MF 4 * with PLL enabled and MF > 4 Internal Clock Cycle Time Instruction Cycle Time Symbol Minimum f TH ETH Maximum 0.48 x TC 0.467 x TC 0.52 x TC 0.533 x TC TL ETL 0.48 x TC 0.467 x TC 2 x TC 0.52 x TC 0.533 x TC TC ICYC (DF /MF) x ETC EXTERNAL CLOCK (EXTAL PIN) The DSP56004 system clock is externally supplied via the EXTAL pin. Timings shown in this document are valid for clock rise and fall times of 3 ns maximum. Table 2-5 External Clock (EXTAL Pin) 50 MHz No. Characteristics Frequency of External Clock (EXTAL Pin) 1 External Clock Input High--EXTAL * with PLL disabled (46.7%-53.3% duty cycle) * with PLL enabled (42.5%-57.5% duty cycle) Pin1 Sym. Min Ef ETH 0 9.3 8.5 ETL Max 50 235500 Min 0 7.1 6.4 Max 66 235500 Min 0 5.8 5.2 Max 81 235500 MHz ns ns 66 MHz 81 MHz Unit 2 External Clock Input Low--EXTAL Pin1 * with PLL disabled (46.7%-53.3% duty cycle) * with PLL enabled (42.5%-57.5% duty cycle) 9.3 8.5 235500 7.1 6.4 235500 5.8 5.2 235500 ns ns MOTOROLA DSP56004/D, Rev. 3 2-5 Specifications Phase Lock Loop (PLL) Characteristics Table 2-5 External Clock (EXTAL Pin) (Continued) 50 MHz No. 3 Characteristics External Clock Cycle Time1 * with PLL disabled * with PLL enabled Instruction Cycle Time = Icyc = 2 x TC1 * with PLL disabled * with PLL enabled 1. 66 MHz Min Max 81 MHz Unit Min Max ns ns ns ns Sym. Min ETC 20 20 40 40 Max 15.15 409600 15.15 409600 819200 30.3 30.3 819200 12.3 12.3 409600 24.7 24.7 819200 4 ICYC Note: External Clock Input High and External Clock Input Low are measured at 50% of the input transition. EXTAL 1 ETH 3 ETC 2 ETL 4 AA0250 Figure 2-1 External Clock Timing PHASE LOCK LOOP (PLL) CHARACTERISTICS Table 2-6 Phase Lock Loop (PLL) Characteristics Characteristics VCO frequency when PLL enabled PLL external capacitor (PCAP pin to VCCP) Note: 1. Expression MF x Ef MF x CPCAP1 @ MF 4 @ MF > 4 Min 10 MF x 340 MF x 380 Max f1 MF x 480 MF x 970 Unit MHz pF pF Cpcap is the value of the PLL capacitor (connected between PCAP pin and VCCP) for MF = 1. The recommended value for Cpcap is 400 pF for MF 4 and 540 pF for MF > 4. The maximum VCO frequency is limited to the internal operation frequency, defined in Table 2-4. 2-6 DSP56004/D, Rev. 3 MOTOROLA Specifications RESET, Stop, Mode Select, and Interrupt Timing RESET, STOP, MODE SELECT, AND INTERRUPT TIMING Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (CL = 50 pF + 2 TTL Loads) All frequencies No. 10 Characteristics Min Minimum RESET assertion width: * PLL disabled * PLL enabled1 Mode Select Setup Time Mode Select Hold Time Minimum Edge-triggered Interrupt Request Assertion Width 25 x TC 2500 x ETC 21 0 13 13 12 x TC + TH Max -- -- -- -- -- -- -- ns ns ns ns ns ns ns Unit 14 15 16 16a Minimum Edge-triggered Interrupt Request Deassertation Width 18 Delay from IRQA, IRQB, NMI Assertion to GPIO Valid Caused by First Interrupt Instruction Execution 22 Delay from General Purpose Output Valid to Interrupt Request Deassertation for Level Sensitive Fast Interrupts--If Second Interrupt Instruction is: 2 * Single Cycle * Two Cycles Duration of IRQA Assertion for Recovery from Stop State Duration for Level Sensitive IRQA Assertion to ensure interrupt service (when exiting "Stop") * Stable External Clock, OMR Bit 6 = 1 * Stable External Clock, PCTL Bit 17 = 1 1. TL - 31 (2 x TC) + TL - 31 12 -- ns ns ns 25 27 6 x TC + TL 12 -- -- ns ns Note: 2. This timing requirement is sensitive to the quality of the external PLL capacitor connected to the PCAP pin. For capacitor values 2 nF, asserting RESET according to this timing requirement will ensure proper processor initialization for capacitors with a C/C < 0.5%. (This is typical for ceramic capacitors.) For capacitor values > 2 nF, asserting RESET according to this timing requirement will ensure proper processor initialization for capacitors with a C/C < 0.01%. (This is typical for Teflon, polystyrene, and polypropylene capacitors.) However, capacitors with values > 2 nF with a C/C > 0.01% may require longer RESET assertion to ensure proper initialization. When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timing 22 applies to prevent multiple interrupt service. To avoid these timing restrictions, the Negative Edge-triggered mode is recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode. VIHR RESET 10 AA0251 Figure 2-2 Reset Timing MOTOROLA DSP56004/D, Rev. 3 2-7 Specifications RESET, Stop, Mode Select, and Interrupt Timing RESET VIHR 14 VIHM 15 VIH IRQA, IRQB, NMI MODA, MODB MODC VILM VIL AA0252 Figure 2-3 Operating Mode Select Timing IRQA, IRQB, NMI 16 IRQA, IRQB, NMI 16A AA0253 Figure 2-4 External Interrupt Timing (Negative Edge-triggered) General Purpose I/O (Output) 18 IRQA IRQB NMI 22 General Purpose I/O AA0254 Figure 2-5 External Level-sensitive Fast Interrupt Timing 25 IRQA AA0255 Figure 2-6 Recovery from Stop State Using IRQA 27 IRQA AA0256 Figure 2-7 Recovery from Stop State Using IRQA Interrupt Service 2-8 DSP56004/D, Rev. 3 MOTOROLA Specifications External Memory Interface (EMI) DRAM Timing EXTERNAL MEMORY INTERFACE (EMI) DRAM TIMING (CL = 50 pF + 2 TTL Loads) Table 2-8 External Memory Interface (EMI) DRAM Timing No. Characteristics Symbol tPC tRAC, tGA tCAC tAA tCLZ tRASP slow fast tRAS slow fast slow fast slow fast slow fast Timing Mode slow fast slow fast slow fast slow fast 50 MHz Expression Min Max Min Max Min Max 4 x TC 3 x TC 7 x TC - 16 5 x TC - 16 3 x TC - 10 2 x TC - 10 80 60 -- -- -- -- -- -- 124 84 50 30 63 43 -- -- -- -- -- -- -- -- -- -- -- 61 46 -- -- -- -- -- -- 0 156 110 95 65 70 40 35 20 30 15 -- -- 90 60 35 20 46 30 -- -- -- -- -- -- -- -- -- -- -- 49.4 37.0 -- -- -- -- -- -- 0 125 87.8 75.4 50.8 56.7 32.0 27.0 14.7 22.0 9.7 -- -- 70.4 45.7 27.0 14.7 36.2 23.8 -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 66 MHz 81 MHz Unit 41 Page Mode Cycle Time 42 RAS or RD Assertion to Data Valid 43 CAS Assertion to Data Valid 44 Column Address Valid to Data Valid 45 CAS Assertion to Data Active 46 RAS Assertion Pulse Width1 (Page Mode Access Only) 47 RAS Assertion Pulse Width (Single Access Only) 48 RAS or CAS Deassertation to RAS Assertion 49 CAS Assertion Pulse Width 50 Last CAS Assertion to RAS Deassertation (Page Mode Access Only) 51 RAS or WR Assertion to CAS Deassertation 52 RAS Assertion to CAS Assertion 53 RAS Assertion to Column Address Valid 3 xTC + TL - 7 -- 2 x TC + TL - 7 -- 0 3 x TC - 11 + n x 4 x TC 2 x TC -11 + n x 3 xTC 7 x TC - 11 5 x TC - 11 5 x TC - 5 3 x TC - 5 3 x TC - 10 2 x TC - 10 3 x TC - 15 2 x TC - 15 0 209 149 129 89 95 55 50 30 45 25 tRP, tCRP tCAS tRSH tCSH, tCWL tRCD tRAD slow fast slow fast slow fast 7 x TC - 15 5 x TC - 15 4 x TC - 13 3 x TC - 13 3 xTC + TH - 13 2 x TC + TH - 13 125 85 67 47 57 37 -- -- -- -- -- -- 91 61 47 32 40 25 -- -- -- -- -- -- 71.4 46.7 36.4 24 30.2 17.9 -- -- -- -- -- -- ns ns ns ns ns ns MOTOROLA DSP56004/D, Rev. 3 2-9 Specifications External Memory Interface (EMI) DRAM Timing Table 2-8 External Memory Interface (EMI) DRAM Timing (Continued) No. Characteristics Symbol tCP Timing Mode 50 MHz Expression Min Max Min Max Min Max TC - 5 15 -- 10 -- 7.3 -- ns 66 MHz 81 MHz Unit 54 CAS Deassertation Pulse Width (Page Mode Access Only) 55 Row Address Valid to RAS Assertion (Row Address Setup Time) 56 RAS Assertion to ROW Address Not Valid (Row Address Hold Time) 57 Column Address Valid to CAS Assertion (Column Address Setup Time) 58 CAS Assertion to Column Address Not Valid (Column Address Hold Time) 59 Last CAS Assertion to Column Address Not Valid (Column Address Hold Time) 60 RAS Assertion to Column Address Not Valid 61 Column Address Valid to RAS Deassertation 62 CAS, RAS, RD, or WR Deassertation to WR or RD Assertion tASR TL - 6 4 -- 2 -- 0.2 -- ns tRAH slow fast 3 x TC + TH - 14 2 x TC + TH - 14 TL - 6 56 36 4 -- -- -- 39 24 2 -- -- -- 29.2 16.9 0.2 -- -- -- ns ns ns tASC tCAH slow fast 3 x TC + TH - 14 2 x TC + TH - 14 56 36 -- -- 39 24 -- -- 29.2 16.9 -- -- ns ns tCAH slow fast 7 x TC + TH - 136 14 4 x TC + TH - 76 14 7 x TC + TH - 136 14 5 x TC + TH - 96 14 3 x TC + TL - 7 63 2 x TC + TL - 7 43 5 x TC - 11 3 x TC - 11 0 89 49 0 -- -- -- -- -- -- -- -- -- 100 54 100 69 46 30 65 35 0 -- -- -- -- -- -- -- -- -- 78.6 41.6 78.6 53.9 36.2 23.9 50.7 26.0 0 -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns tAR slow fast tRAL tRCH, tRRH slow fast slow fast 63 CAS or RD Deassertation tOFF, tGZ to Data Not Valid (Data Hold Time) 64 Random Read or Write Cycle Time (Single Access Only) tRC slow fast 12 x TC 8 x TC 240 160 -- -- 182 121 -- -- 148 98.8 -- -- ns ns 2-10 DSP56004/D, Rev. 3 MOTOROLA Specifications External Memory Interface (EMI) DRAM Timing Table 2-8 External Memory Interface (EMI) DRAM Timing (Continued) No. Characteristics Symbol tRCS tWCH tDS Timing Mode slow fast slow fast 50 MHz Expression Min Max Min Max Min Max 9 x TC - 11 6 x TC - 11 3 x TC - 13 2 x TC - 13 TL - 6 169 109 47 27 4 -- -- -- -- -- 125 80 32 17 2 -- -- -- -- -- 100 63.1 24 11.7 0.2 -- -- -- -- -- ns ns ns ns ns 66 MHz 81 MHz Unit 65 WR Deassertation to CAS Assertion 66 CAS Assertion to WR Deassertation 67 Data Valid to CAS Assertion (Data Setup Time) 68 CAS Assertion to Data Not Valid (Data Hold Time) 69 RAS Assertion to Data Not Valid tDH slow fast 3 x TC + TH - 14 2 x TC + TH - 14 56 36 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 39 24 100 69 47 31 97 67 91 61 40 25 93 63 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 29.2 16.8 78.6 53.9 35.4 23 77.4 52.7 71.5 46.7 30.2 17.9 73.4 48.7 -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns tDHR slow fast 7 x TC + TH - 136 14 5 x TC + TH - 96 14 4 x TC - 14 3 x TC - 14 7 x TC - 9 5 x TC - 9 7 x TC - 15 5 x TC - 15 3 x TC + TH - 13 2 x TC + TH - 13 7 x TC - 13 5 x TC - 13 66 46 131 91 125 85 57 37 127 87 70 WR Assertion to CAS Assertion 71 WR Assertion Pulse Width (Single Cycle Only) 72 RAS Assertion to WR Deassertation (Single Cycle Only) 73 WR Assertion to Data Active tWCS tWP slow fast slow fast slow fast slow fast tWCR 74 RD or WR Assertion to RAS Deassertation (Single Cycle Only) Note: 1. tROH, tRWL slow fast n is the number of successive accesses. n = 2, 3, 4, or 6. MOTOROLA DSP56004/D, Rev. 3 2-11 Specifications External Memory Interface (EMI) DRAM Timing 48 MRAS 47 64 48 74 52 65 49 MCAS 55 53 60 MA0-MA10 Row Address 56 MWR Last Column Address 57 44 61 43 MRD 42 45 MD0-MD7 Data In AA0257 50 59 62 63 Figure 2-8 DRAM Single Read Cycle 2-12 DSP56004/D, Rev. 3 MOTOROLA Specifications External Memory Interface (EMI) DRAM Timing 48 60 MRAS 65 52 49 MCAS 51 55 53 MA0-MA10 Row Address 46 50 48 41 54 54 49 49 61 58 Col. Address 58 Col. Address 59 Last Column Address 56 57 MWR 44 43 MRD 43 42 45 MD0-MD7 45 Data In 57 57 44 43 62 44 63 63 45 Data In Data In 63 AA0263 Figure 2-9 DRAM Page Mode Read Cycle MOTOROLA DSP56004/D, Rev. 3 2-13 Specifications External Memory Interface (EMI) DRAM Timing 64 48 MRAS 47 48 74 52 65 MCAS 50 49 55 53 61 59 60 MA0-MA10 Row Address 56 70 72 Column Address 57 66 62 MWR 71 MRD 69 67 73 68 MD0-MD7 Data Out AA0264 Figure 2-10 DRAM Single Write Cycle 2-14 DSP56004/D, Rev. 3 MOTOROLA Specifications External Memory Interface (EMI) DRAM Timing 48 60 MRAS 46 50 48 65 52 49 MCAS 41 54 54 49 49 51 55 53 MA0-MA10 Row Address 61 58 Col. Address 58 Col. Address 59 Last Column Address 56 57 70 MWR 57 66 57 62 MRD 69 67 73 68 68 67 Data Out Data Out 68 67 Data Out AA0265 MD0-MD7 Figure 2-11 DRAM Page Mode Write Cycle MOTOROLA DSP56004/D, Rev. 3 2-15 Specifications External Memory Interface (EMI) DRAM Refresh Timing EXTERNAL MEMORY INTERFACE (EMI) DRAM REFRESH TIMING (CL = 50 pF + 2 TTL Loads) Table 2-9 External Memory Interface (EMI) DRAM Refresh Timing No. Characteristics Sym. tRP tCPN tRC tRAS tRP Timing Mode slow fast slow fast slow fast slow fast slow fast 50 MHz Exp. Min Max Min Max Min 6 x TC - 7 4 x TC - 7 5 x TC - 7 3 x TC - 7 12 x TC 8 x TC 6 x TC - 9 4 x TC - 9 5 x TC - 5 3 x TC - 5 TC - 7 6 x TC - 15 4 x TC - 15 5 x TC - 11 3 x TC - 11 0 113 73 93 53 240 160 111 71 95 55 13 -- -- -- -- 84 54 71 38 -- -- -- -- 67.1 42.4 54.7 30 148.2 98.8 65.1 40.4 55.7 32 5.3 Max -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns 66 MHz 81 MHz Unit 81 RAS Deassertation to RAS Assertion 82 CAS Deassertation to CAS Assertion 83 Refresh Cycle Time 84 RAS Assertion Pulse Width 85 RAS Deassertation to RAS Assertion for Refresh Cycle1 86 CAS Assertion to RAS Assertion on Refresh Cycle 87 RAS Assertion to CAS Deassertation on Refresh Cycle 88 RAS Deassertation to CAS Assertion on a Refresh Cycle 89 CAS Deassertation to Data Not Valid Note: 1. -- 181.8 -- -- 121.2 -- -- -- -- -- -- 81.9 51.6 70 40 8 -- -- -- -- -- tCSR tCHR slow fast slow fast 105 65 89 49 0 -- -- -- -- -- 75.9 45.6 65 34 0 -- -- -- -- -- 59.1 34.4 50.7 26 0 -- -- -- -- -- ns ns ns ns ns tRPC tOFF This happens when a Refresh Cycle is followed by an Access Cycle. 2-16 DSP56004/D, Rev. 3 MOTOROLA Specifications External Memory Interface (EMI) SRAM Timing 83 81 MRAS 84 85 88 82 MCAS 87 86 89 MD0-MD7 Data In AA0266 Figure 2-12 CAS before RAS Refresh Cycle EXTERNAL MEMORY INTERFACE (EMI) SRAM TIMING (CL = 50 pF + 2 TTL Loads) Table 2-10 External Memory Interface (EMI) SRAM Timing 50 MHz No. Characteristics Symbol tRC, tWC tAS tWP -- tWR Expression Min Max Min Max Min Max 91 Address Valid and CS Assertion Pulse Width 92 Address Valid to RD or WR Assertion 93 RD or WR Assertion Pulse Width 94 RD or WR Deassertation to RD or WR Assertion 95 RD or WR Deassertation to Address not Valid 4 x TC - 11 + Ws x TC TC + TL - 13 2 x TC - 5 + Ws x TC 2 x TC - 11 TH - 6 3 x TC + TL -15 + Ws x TC 2 x TC - 15 + Ws x TC 69 17 35 29 4 -- -- -- -- -- -- -- 55 25 50 10 23 19 2 -- -- -- -- -- -- -- 38 15 38.4 5.5 20 13.7 0.2 -- -- -- -- -- -- -- 28.2 9.7 ns ns ns ns ns ns ns 66 MHz 81 MHz Unit 96 Address Valid to Input Data tAA, tAC Valid 97 RD Assertion to Input Data Valid tOE MOTOROLA DSP56004/D, Rev. 3 2-17 Specifications External Memory Interface (EMI) SRAM Timing Table 2-10 External Memory Interface (EMI) SRAM Timing 50 MHz No. Characteristics Symbol tOHZ Expression Min Max Min Max Min Max 98 RD Deassertation to Data Not Valid (Data Hold Time) 99 Address Valid to WR Deassertation 100 Data Setup Time to WR Deassertation 101 Data Hold Time from WR Deassertation 102 WR Assertion to Data Valid 103 WR Deassertation to Data high impedance1 104 WR Assertion to Data Active Note: 1. 66 MHz 81 MHz Unit 0 0 56 25 4 -- -- 4 -- -- -- -- 14 20 -- 0 39 18 2 -- -- 2 -- -- -- -- 12 18 -- 0 29.2 11.0 0.2 -- -- 0.2 -- -- -- -- 10.2 16.2 -- ns ns ns ns ns ns ns tCW, tAW 3 x TC + TL -14 + Ws x TC tDS (tDW) tDH -- -- -- TC + TL - 5 + Ws x TC TH - 6 TH + 4 TH + 10 TH - 6 This value is periodically sampled and not 100% tested. MA0-MA14 MA15/MCS3 MA16/MCS2/MCAS MA17/MCS1/MRAS MCS0 91 92 94 93 95 RD 94 WR 97 96 98 MD0-MD7 Data In AA0267 Figure 2-13 SRAM Read Cycle 2-18 DSP56004/D, Rev. 3 MOTOROLA Specifications External Memory Interface (EMI) SRAM Timing MA0-MA14 MA15/MCS3 MA16/MCS2/MCAS MA17/MCS1/MRAS MCS0 91 99 95 92 93 WR 94 RD 94 100 102 MD0-MD7 104 Data Out 101 AA0268 103 Figure 2-14 SRAM Write Cycle MOTOROLA DSP56004/D, Rev. 3 2-19 Specifications Serial Audio Interface (SAI) Timing SERIAL AUDIO INTERFACE (SAI) TIMING (CL = 50 pF + 2 TTL Loads) Table 2-11 Serial Audio Interface (SAI) Timing 50 MHz No. Characteristics Mode master slave master slave master slave master slave master slave master slave Expression Min Max Min Max Min Max 111 Minimum Serial Clock Cycle = tSAICC (min) 112 Serial Clock High Period 113 Serial Clock Low Period 114 Serial Clock Rise/Fall Time 115 Data In Valid to SCKR edge (Data In Set-up Time) 116 SCKR Edge to Data In Not Valid (Data In Hold Time) 4 x TC 3 x TC + 5 0.5 x tSAICC - 8 0.35 x tSAICC 0.5 x tSAICC - 8 0.35 x tSAICC 8 0.15 x tSAICC 26 4 0 14 20 12 12 80 65 32 23 32 23 -- -- 26 4 0 14 -- 12 12 -- -- -- -- -- -- 8 10 -- -- -- -- 20 -- -- 61 51 22 18 22 18 -- -- 26 4 0 14 -- 12 12 -- -- -- -- -- -- 8 8 -- -- -- -- 20 -- -- 49.4 42 16.7 14.7 16.7 14.7 -- -- 26 4 0 14 -- 12 12 -- -- -- -- -- -- 8 6.3 -- -- -- -- 20 -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 66 MHz 81 MHz Unit 117 SCKR Edge to Word Select Out master Valid (WSR Out Delay Time) 118 Word Select In Valid to SCKR Edge (WSR In Set-up Time) 119 SCKR Edge to Word Select In Not Valid (WSR In Hold Time) 121 SCKT Edge to Data Out Valid (Data Out Delay Time) slave slave master slave1 slave2 13 40 TH + 34 19 12 12 -- -- -- -- 12 12 13 40 44 19 -- -- -- -- -- -- 12 12 13 40 41 19 -- -- -- -- -- -- 12 12 13 40 40.2 19 -- -- ns ns ns ns ns ns 122 SCKT Edge to Word Select Out master Valid (WST Out Delay Time) 123 Word Select In Valid to SCKT Edge (WST In Set-up Time) 124 SCKT Edge to Word Select In Not Valid (WST In Hold Time) Note: 1. 2. slave slave When the Frequency Ratio between Parallel and Serial clocks is 1:4 or greater When the Frequency Ratio between Parallel and Serial clocks is 1:3 - 1:4 2-20 DSP56004/D, Rev. 3 MOTOROLA Specifications Serial Audio Interface (SAI) Timing 111 112 SCKR (RCKP = 1) 111 113 SCKR (RCKP = 0) 115 SDI0-SDI1 (Data Input) 118 WSR (Input) Valid 117 WSR (Output) AA0269 114 113 114 114 114 112 116 Valid 119 Figure 2-15 SAI Receiver Timing MOTOROLA DSP56004/D, Rev. 3 2-21 Specifications Serial Audio Interface (SAI) Timing 111 112 SCKT (TCKP = 1) 111 113 SCKT (TCKP = 0) 121 SDO0-SDO2 (Data Output) 124 123 WST (Input) Valid 122 WST (Output) AA0270 114 113 114 114 114 112 Figure 2-16 SAI Transmitter Timing 2-22 DSP56004/D, Rev. 3 MOTOROLA Specifications Serial Host Interface (SHI) SPI Protocol Timing SERIAL HOST INTERFACE (SHI) SPI PROTOCOL TIMING (CL = 50 pF; VIHS = 0.7 x VCC, VILS = 0.3 x VCC) Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing No. Characteristics Tolerable Spike Width on Clock or Data In 141 Minimum Serial Clock Cycle = tSPICC(min) For frequency below 33 MHz1 For frequency above 33 MHz1 CPHA = 0, CPHA = 12 Mode Filter Mode bypassed narrow wide 50 MHz Expression Min Max Min Max Min -- -- -- 0 20 100 -- -- -- 0 20 100 -- -- -- Max 0 20 100 ns ns ns 66 MHz 81 MHz Unit master bypassed bypassed narrow wide bypassed narrow wide bypassed narrow wide 4 x TC 6 x TC 1000 2000 3 x TC 3 x TC+ 25 3 x TC + 85 3 x TC + 79 3 x TC + 431 3 x TC + 1022 0.5 x tSPICC -10 TC + 8 TC + 31 TC + 43 TC + TH + 40 TC + TH + 216 TC + TH + 511 0.5 x tSPICC -10 TC + 8 TC + 31 TC + 43 TC + TH + 40 TC + TH + 216 TC + TH + 511 10 2000 -- 120 1000 2000 60 85 145 139 491 1082 50 28 51 63 70 246 541 50 28 51 63 70 246 541 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 2000 -- 91 1000 2000 45 70 130 124 476 1067 35 23 46 58 63 239 534 35 23 46 58 63 239 534 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 2000 -- 74.1 1000 2000 37 62 122 116 468 1059 27.0 20.3 43.3 55.3 58.5 235 530 27.0 20.3 43.3 55.3 58.5 235 550 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10 2000 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns slave CPHA = 1 slave 142 Serial Clock High master Period CPHA = 0, CPHA = 12 slave bypassed narrow wide CPHA = 1 slave bypassed narrow wide 143 Serial Clock Low master Period CPHA = 0, CPHA = 12 slave bypassed narrow wide CPHA = 1 slave bypassed narrow wide 144 Serial Clock Rise/Fall master Time slave MOTOROLA DSP56004/D, Rev. 3 2-23 Specifications Serial Host Interface (SHI) SPI Protocol Timing Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing (Continued) No. Characteristics Mode slave Filter Mode bypassed narrow wide bypassed narrow wide bypassed narrow wide bypassed narrow wide 50 MHz Expression Min Max Min Max Min TC + TH + 35 TC + TH + 35 TC + TH + 35 6 0 0 TC + 6 TC + 70 TC + 197 2 66 193 65 65 65 6 0 0 26 90 217 2 66 193 0 17 32 0 18 33 57 58 68 57 58 68 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 24 41 214 504 41 214 504 70 246 541 58 58 58 6 0 0 21 85 212 2 66 193 0 22 37 0 23 38 47 48 58 47 48 58 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 24 41 214 504 41 214 504 63 239 534 53.5 53.5 53.5 6 0 0 18.3 82.4 209 2 66 193 0 25 40 0 26 41 41.7 42.7 52.7 41.7 42.7 52.7 4 -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 24 41 214 504 41 214 504 58.5 235 530 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 66 MHz 81 MHz Unit 146 SS Assertion to First SCK Edge CPHA = 0 CPHA = 1 slave 147 Last SCK Edge to SS Not Asserted CPHA = 0 CPHA = 13 slave slave 148 Data In Valid to SCK Edge (Data In Set-up Time) master bypassed 0 narrow MAX {(37 - TC), 0} MAX {(52 - TC), wide 0} 0 slave bypassed narrow MAX {(38 - TC), 0} MAX {(53 - TC), wide 0} master bypassed narrow wide slave bypassed narrow wide slave slave 2 2 2 2 2 2 149 SCK Edge to Data In Not Valid (Data In Hold Time) x x x x x x TC + 17 TC + 18 TC + 28 TC + 17 TC + 18 TC + 28 4 24 150 SS Assertion to Data Out Active 151 SS Deassertation to Data high impedance4 152 SCK Edge to Data Out master bypassed Valid (Data Out Delay narrow Time) wide CPHA = 0, CPHA = 12 slave bypassed narrow wide CPHA = 1 slave bypassed narrow wide 41 214 504 41 214 504 TC + TH + 40 TC + TH + 216 TC + TH + 511 2-24 DSP56004/D, Rev. 3 MOTOROLA Specifications Serial Host Interface (SHI) SPI Protocol Timing Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing (Continued) No. Characteristics Mode Filter Mode 50 MHz Expression Min Max Min Max Min 0 57 163 0 57 163 TC + TH + 35 0 57 163 0 57 163 -- -- -- -- -- -- -- 65 0 57 163 0 57 163 -- -- -- -- -- -- -- 58 0 57 163 0 57 163 -- Max -- -- -- -- -- -- 53.5 ns ns ns ns ns ns ns 66 MHz 81 MHz Unit 153 SCK Edge to Data Out master bypassed Not Valid narrow (Data Out Hold Time) wide slave bypassed narrow wide 154 SS Assertion to Data Out Valid CPHA = 0 157 First SCK Sampling Edge to HREQ Output Deassertation slave slave bypassed 3 x TC + TH + 32 -- narrow -- 3 x TC + TH + 209 wide 3 x TC + TH + -- 507 bypassed 2 x TC + TH + 6 56 narrow 2 x TC + TH + 63 113 wide 2 x TC + TH + 219 169 2 x TC + TH + 7 57 102 279 577 -- -- -- -- -- -- 44 101 207 85 262 560 -- -- -- -- -- -- 36.9 93.9 200 75 252 550 -- -- -- ns ns ns ns ns ns 158 Last SCK Sampling Edge to HREQ Output Not Deasserted CPHA = 1 159 SS Deassertation to HREQ Output Not Deasserted CPHA = 0 160 SS Deassertation Pulse Width CPHA = 0 slave slave 45 37.9 ns slave TC + 4 24 -- 19 -- 16.3 -- ns 161 HREQ In Assertion to master First SCK Edge 162 HREQ In Deassertation to Last SCK Sampling Edge (HREQ In Set-up Time) CPHA = 1 master 0.5 x tSPICC+ 2 x TC + 6 0 106 0 -- -- 82 0 -- -- 67.7 0 -- -- ns ns MOTOROLA DSP56004/D, Rev. 3 2-25 Specifications Serial Host Interface (SHI) SPI Protocol Timing Table 2-12 Serial Host Interface (SHI) SPI Protocol Timing (Continued) No. Characteristics Mode Filter Mode 50 MHz Expression Min Max Min Max Min 0 0 -- 0 -- 0 Max -- ns 66 MHz 81 MHz Unit 163 First SCK Edge to master HREQ In Not Asserted (HREQ In Hold Time) Note: 1. 2. 3. 4. For an Internal Clock frequency below 33 MHz, the minimum permissible Internal Clock to Serial Clock frequency ratio is 4:1. For an Internal Clock frequency above 33 MHz, the minimum permissible Internal Clock to Serial Clock frequency ratio is 6:1. In CPHA = 1 mode, the SPI slave supports data transfers at tSPICC = 3 x TC, if the user assures that the HTX is written at least TC ns before the first edge of SCK of each word.In CPHA = 1 mode, the SPI slave supports data transfers at tSPICC = 3 x TC, if the user assures that the HTX is written at least TC ns before the first edge of SCK of each word. When CPHA = 1, the SS line may remain active low between successive transfers. Periodically sampled, not 100% tested SS (Input) 143 142 SCK (CPOL = 0) (Output) 142 143 SCK (CPOL = 1) (Output) 148 149 MISO (Input) MSB Valid 141 144 144 144 141 144 148 LSB Valid 149 152 MOSI (Output) 161 HREQ 153 LSB MSB 163 (Input) AA0271 Figure 2-17 SPI Master Timing (CPHA = 0) 2-26 DSP56004/D, Rev. 3 MOTOROLA Specifications Serial Host Interface (SHI) SPI Protocol Timing SS (Input) 143 142 SCK (CPOL = 0) (Output) 142 143 SCK (CPOL = 1) (Output) 149 MISO (Input) MSB Valid LSB Valid 141 144 144 141 144 144 148 148 149 152 MOSI (Output) 161 163 HREQ 153 LSB 162 MSB (Input) AA0272 Figure 2-18 SPI Master Timing (CPHA = 1) MOTOROLA DSP56004/D, Rev. 3 2-27 Specifications Serial Host Interface (SHI) SPI Protocol Timing SS (Input) 143 142 SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 154 150 MISO (Output) 148 149 MOSI (Input) HREQ MSB Valid LSB Valid 141 144 144 160 147 142 143 144 141 144 153 MSB 152 153 151 LSB 148 149 157 (Output) 159 AA0273 Figure 2-19 SPI Slave Timing (CPHA = 0) 2-28 DSP56004/D, Rev. 3 MOTOROLA Specifications Serial Host Interface (SHI) SPI Protocol Timing SS (Input) 143 142 SCK (CPOL = 0) (Input) 146 SCK (CPOL = 1) (Input) 152 150 MISO (Output) 148 149 MOSI (Input) HREQ MSB Valid LSB Valid 141 144 144 147 142 143 144 144 152 MSB 153 LSB 148 151 149 157 (Output) 158 AA0274 Figure 2-20 SPI Slave Timing (CPHA = 1) MOTOROLA DSP56004/D, Rev. 3 2-29 Specifications Serial Host Interface (SHI) I2C Protocol Timing SERIAL HOST INTERFACE (SHI) I2C PROTOCOL TIMING (VIHS = 0.7 x VCC, VILS = 0.3 x VCC) (VOHS = 0.8 x VCC, VOLS = 0.2 x VCC) (RP (min) = 1.5 k) Table 2-13 SHI I2C Protocol Timing Standard I2C (CL = 400 pF, RP = 2 k, 100 kHz) All frequencies No. -- Characteristics Tolerable Spike Width on SCL or SDA Filters Bypassed Narrow Filters Enabled Wide Filters Enabled Minimum SCL Serial Clock Cycle Bus Free Time Start Condition Set-up Time Start Condition Hold Time SCL Low Period SCL High Period SCL and SDA Rise Time SCL and SDA Fall Time Data Set-up Time Data Hold Time SCL Low to Data Out Valid Stop Condition Set-up Time Refer to the DSP56004 modes. Symbol Min -- -- -- tSCL tBUF tSU;STA tHD;STA tLOW tHIGH tr tf tSU;DAT tHD;DAT tVD;DAT tSU;STO 10.0 4.7 4.7 4.0 4.7 4.0 -- -- 250 0.0 -- 4.0 Max 0 20 100 -- -- -- -- -- -- 1.0 0.3 -- -- 3.4 -- Unit ns ns ns s s s s s s s s ns ns s s 171 172 173 174 175 176 177 178 179 180 182 183 Note: User's Manual for a detailed description of how to use the different filtering 2-30 DSP56004/D, Rev. 3 MOTOROLA Specifications Serial Host Interface (SHI) I2C Protocol Timing The Programmed Serial Clock Cycle, t I2CCP , is specified by the value of the HDM5- HDM0 and HRS bits of the HCKR (SHI Clock control Register). The expression for t I2CCP is: t I CCP 2 = [ Tc x 2 x ( HDM[5:0] + 1 ) x ( 7 x ( 1 - HRS ) + 1 ) ] where * * * HRS is the Prescaler Rate Select bit. When HRS is cleared, the fixed divide-byeight prescaler is operational. When HRS is set, the prescaler is bypassed. HDM5-HDM0 are the Divider Modulus Select bits. A divide ratio from 1 to 64 (HDM5-HDM0 = 0 to $3F) may be selected. In I2C mode, you may select a value for the Programmed Serial Clock Cycle from (HDM5-HDM0 = 2, HRS = 1) to 6 x TC (HDM5-HDM0 = $3F, HRS = 0). 1024 x TC The DSP56004 provides an improved I2C bus protocol. In addition to supporting the 100 kHz I2C bus protocol, the SHI in I2C mode supports data transfers at up to 1000 kHz. The actual maximum frequency is limited by the bus capacitances (CL),the pullup resistors (RP), (which affect the rise and fall time of SDA and SCL, (see table below)), and by the input filters. Consideration for programming the SHI Clock Control Register (HCKR) - Clock Divide Ratio: the master must generate a bus free time greater than T172 slave when operating with a DSP56004 SHI I2C slave. The table below describes a few examples: Table 2-14 Considerations for Programming the SHI Clock control Register (HCKR) Conditions to be Considered Resulting Limitations Bus Load Master Operating Freq. Slave Operating Freq. Master Filter Mode Bypassed Narrow Wide Slave Filter Mode T172 Slave Min. Permissible tI CCP 2 T172 Master 41 ns 66 ns 103 ns Maximum I2C Serial Frequency 1010 kHz 825 kHz 634 kHz CL = 50 pF, RP = 2 k 81 MHz 81 MHz Bypassed 36 ns Narrow 60 ns Wide 95 ns 52 x TC 56 x TC 62 x TC MOTOROLA DSP56004/D, Rev. 3 2-31 Specifications Serial Host Interface (SHI) I2C Protocol Timing Example: for CL = 50 pF, RP = 2 k, f = 88 MHz, Bypassed Filter mode: The master, when operating with a DSP56004 SHI I2C slave with an 88 MHz operating frequency, must generate a bus free time greater than 36 ns (T172 slave). Thus, the minimum permissible tI2CCP is 56 x TC which gives a bus free time of at least 41 ns (T172 master). This implies a maximum I2C serial frequency of 1010 kHz. In general, bus performance may be calculated from the CL and RP of the bus, the Input Filter modes and operating frequencies of the master and the slave. Table 2-15 contains the expressions required to calculate all relevant performance timing for a given CL and RP. Table 2-15 SHI Improved I2C Protocol Timing Improved I2C (CL = 50 pF, RP = 2 k) Filter Mode bypassed narrow wide tSCL master bypassed 2 No. Char. Sym. Mode Expression U n Min Max Min Max Min Max i t -- -- -- 0 20 100 -- -- -- -- 1007 0 20 100 -- -- -- -- 989 0 ns 20 ns 100 ns -- ns 50 MHz2 66 MHz3 81 MHz4 -- Tolerable Spike Width on SCL or SDA 171 SCL Serial Clock Cycle 0 20 100 narrow wide slave bypassed narrow wide 172 Bus Free Time tBUF master bypassed narrow wide slave bypassed narrow wide bypassed narrow wide t I CCP + 3 x 1050 TC +72 +tr t I CCP + 3 x TC + 1263 245 + tr t I CCP + 3 x TC + 1593 535 + tr 4 x TC + TH + 500 172 + tr 4 x TC + TH + 694 366 + tr 4 x TC + TH + 976 648 + tr 2 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1225 1591 478 672 954 46 68 102 41 65 100 12 50 150 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1212 1576 466 660 942 41.1 65.8 103 35.7 59.7 94.7 12 50 150 -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.5 x t I CCP - 42 - tr 0.5 x t I CCP - 42 - tr 0.5 x t I CCP - 42 - tr 2 x TC + 11 2 x TC + 35 2 x TC + 70 2 2 2 60 80 100 51 75 110 12 50 150 173 Start Condition Set-up Time tSU;STA slave 12 50 150 2-32 DSP56004/D, Rev. 3 MOTOROLA Specifications Serial Host Interface (SHI) I2C Protocol Timing Table 2-15 SHI Improved I2C Protocol Timing (Continued) Improved I2C (CL = 50 pF, RP = 2 k) Filter Mode bypassed narrow wide slave bypassed narrow wide bypassed narrow wide slave bypassed narrow wide bypassed narrow wide slave bypassed narrow wide U n Min Max Min Max Min Max i t 332 352 372 71 150 250 338 358 378 352 564 864 379 544 776 49 68 80 -- -- -- -- 28 80 94 -- -- -- -- -- -- 238 2000 20 2000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 318 340 378 59 138 238 324 346 384 342 554 854 375 523 773 37 56 68 -- -- -- -- 23 75 89 -- -- -- -- -- -- 238 2000 20 2000 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 313 338 375 51.9 131 231 319 344 381 337 536 849 365 514 763 30 49 61 -- -- -- -- 20 72 86 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 50 MHz2 66 MHz3 81 MHz4 No. Char. Sym. Mode Expression 0.5 x t I CCP + 12 - tf 0.5 x t I CCP + 12 - tf 0.5 x t I CCP + 12 - tf 2 x TC + TH + 21 2 x TC + TH + 100 2 x TC + TH + 200 2 2 2 174 Start Condition Hold Time tHD;STA master 175 SCL Low Period tLOW master 0.5 x t I CCP + 18 - tf 0.5 x t I CCP + 18 - tf 0.5 x t I CCP + 18 - tf 2 x TC + 74 + tr 2 x TC + 286 + tr 2 x TC + 586 + tr 2 2 2 176 SCL High Period tHIGH master 0.5 x t I CCP + 2 x TC + 19 0.5 x t I CCP + 2 x TC + 144 0.5 x t I CCP + 2 x TC + 356 2 x TC + TH - 1 2 x TC + TH + 18 2 x TC + TH + 30 2 2 2 177 SCL Rise Time Output1 Input tr 1.7 x RP x (CL + 20) 2000 20 + 0.1 x (CL- 50) 2000 bypassed narrow wide TC + 8 TC + 60 TC + 74 238 ns 2000 ns 20 ns 178 SCL Fall Time Output1 Input tf 2000 ns -- -- -- ns ns ns 179 Data Set-up Time tSU;DAT MOTOROLA DSP56004/D, Rev. 3 2-33 Specifications Serial Host Interface (SHI) I2C Protocol Timing Table 2-15 SHI Improved I2C Protocol Timing (Continued) Improved I2C (CL = 50 pF, RP = 2 k) Filter Mode bypassed narrow wide bypassed narrow wide bypassed narrow wide slave bypassed narrow wide bypassed narrow wide U n Min Max Min Max Min Max i t 0 0 0 -- -- -- 381 459 613 11 50 150 0 0 0 -- -- -- 349 522 813 -- -- -- -- -- -- -- -- -- 0 0 0 -- -- -- 359 440 592 11 50 150 0 0 0 -- -- -- 339 512 803 -- -- -- -- -- -- -- -- -- 0 0 0 -- -- -- 351 433 584 11 50 150 0 0 0 -- -- -- ns ns ns 50 MHz2 66 MHz3 81 MHz4 No. Char. Sym. Mode Expression 180 Data Hold Time tHD;DAT 0 0 0 2 x TC + 71 + tr 2 x TC + 244 + tr 2 x TC + 535 + tr 0.5 x t I CCP + TC + TH + 11 0.5 x t I CCP + TC + TH + 69 0.5 x t I CCP + TC + TH + 183 11 50 150 2 2 2 182 SCL Low to Data tVD;DAT Out Valid 183 Stop Condition Set-up Time tSU;STO master 344 ns 507 ns 798 ns -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns 184 HREQ In Deassertation to Last SCL Edge (HREQ In Set-up Time) 186 First SCL Sampling Edge to HREQ Output Deassertation 187 Last SCL Edge to HREQ Output Not Deasserted 188 HREQ In Assertion to First SCL Edge master 0 0 0 slave bypassed narrow wide bypassed narrow wide bypassed narrow wide 3 x TC + TH + 32 3 x TC + TH + 209 3 x TC + TH + 507 -- -- -- 102 279 577 -- -- -- -- -- -- -- -- -- 44 101 207 688 733 809 85 262 560 -- -- -- -- -- -- -- -- -- 37 93.9 200 673 722 796 75 ns 252 ns 550 ns -- -- -- -- -- -- ns ns ns ns ns ns slave 2 x TC + TH + 6 56 2 x TC + TH + 63 113 2 x TC + TH + 169 219 t I CCP + 2 x TC + 6 726 t I CCP + 2 x TC + 6 766 t I CCP + 2 x TC + 6 846 2 2 2 master 2-34 DSP56004/D, Rev. 3 MOTOROLA Specifications Serial Host Interface (SHI) I2C Protocol Timing Table 2-15 SHI Improved I2C Protocol Timing (Continued) Improved I2C (CL = 50 pF, RP = 2 k) Filter Mode U n Min Max Min Max Min Max i t 0 -- 0 -- 0 -- ns 50 MHz2 66 MHz3 81 MHz4 No. Char. Sym. Mode Expression 189 First SCL Edge to HREQ In Not Asserted (HREQ In Hold Time) Note: 1. 2. 2 master 0 3. 4. 5. CL is in pF, RP is in k, and result is in ns. A t I CCP of 34 x TC (the maximum permitted for the given bus load) was used for the calculations in the Bypassed Filter mode. A t I CCP of 36 x TC (the maximum permitted for the given bus load) was used for the calculations in the Narrow Filter mode. A t I CCP of 40 x TC (the maximum permitted for the given bus load) was used for the calculations in the Wide Filter mode. A t I CCP of 43 x TC (the maximum permitted for the given bus load) was used for the calculations in the Bypassed Filter mode. A t I CCP of 46 x TC (the maximum permitted for the given bus load) was used for the calculations in the Narrow Filter mode. A t I CCP of 51 x TC (the maximum permitted for the given bus load) was used for the calculations in the Wide Filter mode. A t I CCP of 52 x TC (the maximum permitted for the given bus load) was used for the calculations in the Bypassed Filter mode. A t I CCP of 56 x TC (the maximum permitted for the given bus load) was used for the calculations in the Narrow Filter mode. A t I CCP of 62 x TC (the maximum permitted for the given bus load) was used for the calculations in the Wide Filter mode. Refer to the DSP56004 User's Manual for a detailed description of how to use the filtering modes. 2 2 2 2 2 2 2 2 171 173 SCL 177 172 SDA Stop Start MSB 176 175 178 179 180 LSB ACK Stop 174 188 HREQ 189 186 184 182 183 187 AA0275 Figure 2-21 I2C Timing MOTOROLA DSP56004/D, Rev. 3 2-35 Specifications General Purpose I/O (GPIO) Timing GENERAL PURPOSE I/O (GPIO) TIMING (CL = 50 pF + 2 TTL Loads) Table 2-16 GPIO Timing All frequencies No. Characteristics Expression Min 201 202 203 204 EXTAL Edge to GPIO Out Valid (GPIO Out Delay Time) EXTAL Edge to GPIO Out Not Valid (GPIO Out Hold Time) GPIO In Valid to EXTAL Edge (GPIO In Set-up Time) EXTAL Edge to GPIO In Not Valid (GPIO In Hold Time) 26 2 10 6 -- 2 10 6 Max 26 -- -- -- ns ns ns ns Unit EXTAL (Input) (Note 1) GPIO0- GPIO3 (Output) 203 GPIO0- GPIO3 (Input) Note: Valid 204 201 202 1. Valid when the ratio between EXTAL frequency and internal clock frequency equals 1 AA0276 Figure 2-22 GPIO Timing 2-36 DSP56004/D, Rev. 3 MOTOROLA Specifications On-Chip Emulation (OnCETM) Timing ON-CHIP EMULATION (OnCETM) TIMING (CL = 50 pF + 2 TTL Loads) Table 2-17 OnCE Timing All frequencies No. Characteristics Min 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 DSCK Low DSCK High DSCK Cycle Time DR Asserted to DSO (ACK) Asserted DSCK High to DSO Valid DSCK High to DSO Invalid DSI Valid to DSCK Low (Set-up) DSCK Low to DSI Invalid (Hold) Last DSCK Low to OS0-OS1, ACK Active DSO (ACK) Asserted to First DSCK High DSO (ACK) Assertion Width DSO (ACK) Asserted to OS0-OS1 High Impedance1 OS0-OS1 Valid to EXTAL Transition #2 EXTAL Transition #2 to OS0-OS1 Invalid Last DSCK Low of Read Register to First DSCK High of Next Command Last DSCK Low to DSO Invalid (Hold) DR Assertion to EXTAL Transition #2 for Wake Up from Wait State EXTAL Transition #2 to DSO After Wake Up from Wait State 40 40 200 5 TC -- 3 15 3 3 TC + TL 2 TC 4 TC + TH - 3 -- T C - 21 0 7 TC + 10 3 10 17 TC Max -- -- -- -- 42 -- -- -- -- -- 5 TC + 7 0 -- -- -- -- TC - 10 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit MOTOROLA DSP56004/D, Rev. 3 2-37 Specifications On-Chip Emulation (OnCETM) Timing Table 2-17 OnCE Timing (Continued) All frequencies No. Characteristics Min 248 DR Assertion Width * to recover from WAIT * to recover from WAIT and enter Debug mode DR Assertion to DSO (ACK) Valid (Enter Debug mode) After Asynchronous Recovery from Wait State DR Assertion Width to Recover from STOP2 * Stable External Clock, OMR Bit 6 = 0 * Stable External Clock, OMR Bit 6 = 1 * Stable External Clock, PCTL Bit 17 = 1 DR Assertion Width to Recover from STOP and enter Debug mode2 * Stable External Clock, OMR Bit 6 = 0 * Stable External Clock, OMR Bit 6 = 1 * Stable External Clock, PCTL Bit 17 = 1 DR Assertion to DSO (ACK) Valid (Enter Debug mode) After Recovery from Stop State2 * Stable External Clock, OMR Bit 6 = 0 * Stable External Clock, OMR Bit 6 = 1 * Stable External Clock, PCTL Bit 17 = 1 1. 2. Maximum TL Periodically sampled, not 100% tested Unit Max 15 13 TC + 15 17 TC 12 TC - 15 -- -- ns ns ns 249 250A 15 15 15 65548 TC + TL 20 TC + TL 13 TC + TL ns ns ns 250B 65549 TC + TL 21 TC + TL 14 TC + TL -- -- -- ns ns ns 251 65553 TC + TL 25 TC + TL 18 TC + TL -- -- -- ns ns ns Note: 246 230 DSCK (input) 231 232 246 AA0277 Figure 2-23 DSP56004 OnCE Serial Clock Timing 2-38 DSP56004/D, Rev. 3 MOTOROLA Specifications On-Chip Emulation (OnCETM) Timing DR (Input) 233 DSO (Output) 240 ACK AA0278 Figure 2-24 DSP56004 OnCE Acknowledge Timing DSCK (Input) DSO (Output) 236 DSI (Input) Note: 1. High Impedance, external pull-down resistor (Note 1) AA0279 (Last) (OS1) 237 238 (ACK) (OS0) Figure 2-25 DSP56004 OnCE Data I/O to Status Timing DSCK (Input) 234 DSO (Output) Note: 1. High Impedance, external pull-down resistor 235 (Last) 245 (Note 1) (OS0) AA0280 Figure 2-26 DSP56004 OnCE Read Timing OS1 (Output) 241 DSO (Output) 240 239 (Note 1) (DSCK Input) (DSO Output) (DSI Input) OS0 (Output) 241 Note: (Note 1) 236 237 AA0281 1. High Impedance, external pull-down resistor Figure 2-27 DSP56004 OnCE Data I/O Status Timing MOTOROLA DSP56004/D, Rev. 3 2-39 Specifications On-Chip Emulation (OnCETM) Timing EXTAL (Note 2) 242 OS0-OS1 (Output) (Note 1) Note: 243 AA0282 1. High Impedance, external pull-down resistor 2. Valid when the ratio between EXTAL frequency and clock frequency equals 1 Figure 2-28 DSP56004 OnCE EXTAL to Status Timing DSCK (Input) (Next Command) 244 AA0283 Figure 2-29 DSP56004 OnCE DSCK Next Command After Read Register Timing T0, T2 T1, T3 248 DR EXTAL (Input) 246 DSO (Output) AA0284 247 Figure 2-30 Synchronous Recovery from Wait State 248 DR (Input) 249 DSO (Output) AA0285 Figure 2-31 Asynchronous Recovery from Wait State 2-40 DSP56004/D, Rev. 3 MOTOROLA Specifications On-Chip Emulation (OnCETM) Timing 250 DR (Input) 251 DSO (Output) AA0286 Figure 2-32 Asynchronous Recovery from Stop State MOTOROLA DSP56004/D, Rev. 3 2-41 Specifications On-Chip Emulation (OnCETM) Timing 2-42 DSP56004/D, Rev. 3 MOTOROLA SECTION PACKAGING PIN-OUT AND PACKAGE INFORMATION 3 This section provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated. The DSP56004 is available in an 80-pin Plastic Quad Flat Pack (PQFP) package. MOTOROLA DSP56004/D, Rev. 3 3-1 Packaging Pin-out and Package Information PQFP Package Description Top and bottom views of the PQFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs. DR MD7 MD6 MD5 MD4 GNDD MD3 MD2 MD1 VCCD MD0 GNDD GPIO3 GPIO2 GPIO1 GPIO0 MRD MWR MA17/MCS1/MRAS MA16/MCS2/MCAS 61 DSCK/OS1 DSI/OS0 DSO SDI0 SDI1 WSR GNDS VCCQ GNDQ SCKR WST SCKT VCCS SDO0 SDO1 SDO2 GNDS HREQ SS/HA2 MOSI/HA0 41 (Top View) Orientation Mark 1 21 VCCS MODC/NMI MODB/IRQB MODA/IRQA RESET MISO/SDA GNDS VCCP PCAP GNDP PINIT GNDQ VCCQ EXTAL SCK/SCL MA0 MA1 MA2 MA3 GNDA Note: An OVERBAR indicates the signal is asserted when the voltage = ground (active low). To simplify locating the pins, each fifth pin is shaded in the illustration. Figure 3-1 Top View 3-2 GNDA MCS0 MA15/MCS3 MA14 MA13 VCCA MA12 GNDA VCCQ GNDQ MA11 MA10 MA9 MA8 GNDA MA7 VCCA MA6 MA5 MA4 DSP56004/D, Rev. 3 MOTOROLA Packaging Pin-out and Package Information VCCS MODC/NMI MODB/IRQB MODA/IRQA RESET MISO/SDA GNDS VCCP PCAP GNDP PINIT GNDQ VCCQ EXTAL SCK/SCL MA0 MA1 MA2 MA3 GNDA 41 MOSI/HA0 SS/HA2 HREQ GNDS SDO2 SDO1 SDO0 VCCS SCKT WST SCKR GNDQ VCCQ GNDS WSR SDI1 SDI0 DSO DSI/OS0 DSCK/OS1 61 (Bottom View) Orientation Mark 21 1 VCCA MA7 GNDA MA8 MA9 MA10 MA11 GNDQ VCCQ GNDA MA12 VCCA MA13 MA14 MA15/MCS3 MCS0 GNDA DR MD7 MD6 MD5 MD4 GNDD MD3 MD2 MD1 VCCD MD0 GNDD GPIO3 GPIO2 GPIO1 GPIO0 MRD MWR MA17/MCS1/MRAS MA16/MCS2/MCAS Note: An OVERBAR indicates the signal is asserted when the voltage = ground (active low). To simplify locating the pins, each fifth pin is shaded in the illustration. Figure 3-2 Bottom View MOTOROLA MA4 MA5 MA6 DSP56004/D, Rev. 3 3-3 Packaging Pin-out and Package Information Table 3-1 DSP56004 Pin Identification by Pin Number Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Signal Name GNDA MCS0 MA15/MCS3 MA14 MA13 VCCA MA12 GNDA VCCQ GNDQ MA11 MA10 MA9 MA8 GNDA MA7 VCCA MA6 MA5 MA4 GNDA MA3 MA2 MA1 MA0 SCK/SCL EXTAL Pin # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Signal Name VCCQ GNDQ PINIT GNDP PCAP VCCP GNDS MISO/SDA RESET MODA/IRQA MODB/IRQB MODC/NMI VCCS MOSI/HA0 SS/HA2 HREQ GNDS SDO2 SDO1 SDO0 VCCS SCKT WST SCKR GNDQ VCCQ GNDS Pin # 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Signal Name WSR SDI1 SDI0 DSO DSI/OS0 DSCK/OS1 DR MD7 MD6 MD5 MD4 GNDD MD3 MD2 MD1 VCCD MD0 GNDD GPIO3 GPIO2 GPIO1 GPIO0 MRD MWR MA17/MCS1/ MRAS MA16/MCS2/ MCAS 3-4 DSP56004/D, Rev. 3 MOTOROLA Packaging Pin-out and Package Information Table 3-2 DSP56004 Pin Identification by Signal Name Signal Name DR DSCK DSI DSO EXTAL GNDA GNDA GNDA GNDA GNDD GNDD GNDP GNDQ GNDQ GNDQ GNDS GNDS GNDS GPIO0 GPIO1 GPIO2 GPIO3 HA0 HA2 HREQ IRQA IRQB MA0 MA1 MA2 MA3 MA4 Pin # 61 60 59 58 27 1 8 15 21 66 72 31 10 29 52 34 44 54 76 75 74 73 41 42 43 37 38 25 24 23 22 20 Signal Name MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 MA15 MA16 MA17 MCAS MCS0 MCS1 MCS2 MCS3 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MISO MODA MODB MODC MOSI MRAS Pin # 19 18 16 14 13 12 11 7 5 4 3 80 79 80 2 79 80 3 71 69 68 67 65 64 63 62 35 37 38 39 41 79 Signal Name MRD MWR NMI OS0 OS1 PCAP PINIT RESET SCK SCKR SCKT SCL SDA SDI0 SDI1 SDO0 SDO1 SDO2 SS VCCA VCCA VCCD VCCP VCCQ VCCQ VCCQ VCCS VCCS WSR WST Pin # 77 78 39 59 60 32 30 36 26 51 49 26 35 57 56 47 46 45 42 6 17 70 33 9 28 53 40 48 55 50 MOTOROLA DSP56004/D, Rev. 3 3-5 Packaging Pin-out and Package Information Table 3-3 DSP56004 Power Supply Pins Pin # 6 17 1 8 15 21 70 66 72 9 28 53 10 29 52 33 31 40 48 34 44 54 GNDS VCCP GNDP VCCS Serial Ports PLL GNDQ VCCQ Internal Logic VCCD GNDD Data Bus Buffers GNDA Signal Name VCCA Circuit Supplied Address Bus Buffers 3-6 DSP56004/D, Rev. 3 MOTOROLA Packaging Pin-out and Package Information L 60 61 41 40 DS DS -AL -BB A-B C A-B V M M H A-B B B S S P -A,B,DDETAIL A 21 0.20 0.05 0.20 DETAIL A 80 1 -D0.20 0.05 M 20 F A C A-B S DS A-B S 0.20 M J A-B S DS N D H E C -CSEATING PLANE M DETAIL C -H0.01 DATUM PLANE 0.20 M C A-B S DS SECTION B-B H G M CASE 841B-01 ISSUE O U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. DIM A B C D E F G H J K L M N P Q R S T U V W X MILLIMETERS MIN MAX 13.90 14.10 13.90 14.10 2.15 2.45 0.22 0.38 2.00 2.40 0.22 0.33 0.65 BSC 0.25 0.13 0.23 0.65 0.95 12.35 BSC 55 105 0.13 0.17 0.325 BSC 05 75 0.13 0.30 16.95 17.45 0.13 05 16.95 17.45 0.35 0.45 1.6 REF T DATUM PLANE -H- R K W X DETAIL C Q Figure 3-3 80-pin Plastic Quad Flat Pack (PQFP) Mechanical Information MOTOROLA DSP56004/D, Rev. 3 3-7 Packaging Ordering Drawings ORDERING DRAWINGS Complete mechanical information regarding DSP56004 packaging is available by facsimile through Motorola's MfaxTM system. Call the following number to obtain information by facsimile: (602) 244-6591 The Mfax automated system requests the following information: * * The receiving facsimile telephone number including area code or country code The caller's Personal Identification Number (PIN) Note: For first time callers, the system provides instructions for setting up a PIN, which requires entry of a name and telephone number. * The type of information requested: - - - - Instructions for using the system A literature order form Specific part technical information or data sheets Other information described by the system messages A total of three documents may be ordered per call. The DSP56004 80-pin PQFP package mechanical drawing is referenced as 841B-01. 3-8 DSP56004/D, Rev. 3 MOTOROLA SECTION 4 DESIGN CONSIDERATIONS THERMAL DESIGN CONSIDERATIONS An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: T J = T A + ( P D x R JA ) Where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: R JA = R JC + R CA Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board, or otherwise change the thermal dissipation capability of the area surrounding the device on a Printed Circuit Board. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the Printed Circuit Board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. MOTOROLA DSP56004/D, Rev. 3 4-1 Design Considerations Thermal Design Considerations The thermal performance of plastic packages is more dependent on the temperature of the Printed Circuit Board to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: * To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ - TT)/PD. * * As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, Thermal Characterization Parameter or JT, has been defined to be (TJ - TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. 4-2 DSP56004/D, Rev. 3 MOTOROLA Design Considerations Electrical Design Considerations ELECTRICAL DESIGN CONSIDERATIONS CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC). Use the following list of recommendations to assure correct DSP operation: * * Provide a low-impedance path from the board power supply to each VCC pin on the DSP, and from the board ground to each GND pin. Use at least four 0.01-0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 0.5 in per capacitor lead. Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VCC and GND. Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the IRQA, IRQB, and NMI pins. Maximum Printed Circuit Board (PCB) trace lengths on the order of 6 inches are recommended. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. All inputs must be terminated (i.e., not allowed to float) using CMOS levels, except as noted in Section 1. Take special care to minimize noise levels on the VCCP and GNDP pins. If multiple DSP56004 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to synchronous operation of the devices. * * * * * * * MOTOROLA DSP56004/D, Rev. 3 4-3 Design Considerations Power Consumption Considerations POWER CONSUMPTION CONSIDERATIONS Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are described in this section. Most of the current consumed by CMOS devices is Alternating Current (AC), which is charging and discharging the capacitances of the pins and internal nodes. Current consumption is described by the formula: Equation 3: I = C x V x f where: C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle Example 4-1 Current Consumption For an I/O pin loaded with 50 pF capacitance, operating at 5.5 V, and with a 81 MHz clock, toggling at its maximum possible rate (20 MHz), the current consumption is: Equation 4: I = 50 x 10 - 12 x 5.5 x 20 x 10 = 5.5mA 6 The Maximum Internal Current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation conditions, which is not necessarily a real application case. The Typical Internal Current (ICCItyp) value reflects the average switching of the internal buses on typical operating conditions. For applications that require very low current consumption: * * * * * Minimize the number of pins that are switching. Minimize the capacitive load on the pins. Connect the unused inputs to pull-up or pull-down resistors. Disable unused peripherals. Disable unused pin activity. 4-4 DSP56004/D, Rev. 3 MOTOROLA Design Considerations Power Consumption Considerations Current consumption test code: org p:RESET jmp org movep move move move move nop rep move rep mov clr move rep mac move jmp nop jmp MAIN p:MAIN #$180000,x:$FFFD #0,r0 #0,r4 #$00FF,m0 #$00FF,m4 #256 r0,x:(r0)+ #256 r4,y:(r4)+ a l:(r0)+,a #30 x0,y0,a x:(r0)+,x0 a,p:(r5) TP1 MAIN y:(r4)+,y0 TP1 MOTOROLA DSP56004/D, Rev. 3 4-5 Design Considerations Power-Up Considerations POWER-UP CONSIDERATIONS To power-up the device properly, ensure that the following conditions are met: * * * * Stable power is applied to the device according to the specifications in Table 2-3 (DC Electrical Characteristics). The external clock oscillator is active and stable. RESET is asserted according to the specifications in Table 2-7 (Reset, Stop, Mode Select, and Interrupt Timing). The following input pins are driven to valid voltage levels: DR, PINIT, MODA, MODB, and MODC. Care should be taken to ensure that the maximum ratings for all input voltages obey the restrictions on Table 2-1 (Maximum Ratings), at all phases of the power-up procedure. This may be achieved by powering the external clock, hardware reset, and mode selection circuits from the same power supply that is connected to the power supply pins of the chip. At the beginning of the hardware reset procedure, the device might consume significantly more current than the specified typical supply current. This is because of contentions among the internal nodes being affected by the hardware reset signal until they reach their final hardware reset state. 4-6 DSP56004/D, Rev. 3 MOTOROLA SECTION 5 ORDERING INFORMATION Consult a Motorola Semiconductor sales office or authorized distributor to determine product availability and to place an order. Table 5-1 Ordering Information Part DSP56004 Supply Voltage 5V Package Type Quad Flat Pack (QFP) Pin Count 80 Frequency (MHz) 50 66 81 DSP56004ROM1 5V Quad Flat Pack (QFP) 80 50 66 81 Note: 1. Order Number DSP56004FJ50 DSP56004FJ66 DSP56004FJ81 Customer Specific Customer Specific Customer Specific For additional information on future part development, or to request specific ROM-based support, call your local Motorola Semiconductor sales office or authorized distributor. MOTOROLA DSP56004/D, Rev. 3 5-1 OnCE, Mfax, and Symphony are trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/Europe/Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 303-675-2140 1 (800) 441-2447 Asia/Pacific: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-26629298 Technical Resource Center: 1 (800) 521-6274 DSP Helpline dsphelp@dsp.sps.mot.com Internet: http://www.motorola-dsp.com Japan: Nippon Motorola Ltd. Tatsumi-SPD-JLDC 6F Seibu-Butsuryu-Center 3-14-2 Tatsumi Koto-Ku Tokyo 135, Japan 81-3-3521-8315 MfaxTM: RMFAX0@email.sps.mot.com TOUCHTONE (602) 244-6609 US & Canada ONLY (800) 774-1848 |
Price & Availability of DSP56004
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |